PXFERGATE
Transfer-gate with active-low enable
Description
Connections
Parameters
Modelica Standard Library
The PXFERGATE component models a tristate buffer with an active-low enable input.
The truth table for the device is
DataIn
Enable
DataOut
*
U
X
UX
0
1
Z
W
L
H
-
where UX={UdataIn=UXotherwise.
The tHL and tLH parameters specify the output transition delay. If the signal goes from low to high, the delay to the output is tLH; if the signal width is less than tLH then the output does not change. Conversely for tHL.
Name
Modelica ID
enable
Logic input; high enables the output
x
Logic input
y
Logic output
Default
Units
tHL
s
High to low transition delay
tLH
Low to high transition delay
The component described in this topic is from the Modelica Standard Library. To view the original documentation, which includes author and copyright information, click here.
See Also
Digital Components
Digital Tristates
Electrical Library
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